I. Field of the Disclosure
The technology of the disclosure relates generally to memory bandwidth compression, and, in particular, to memory bandwidth compression in memory architectures supporting a chipkill-correct error correcting code (ECC) mechanism.
II. Background
As applications executing in a processor-based system increase in terms of complexity and resource requirements, a lack of available memory bandwidth may impose a constraint on system performance. If accesses to an external memory reach memory bandwidth limits, a memory controller of the processor-based system may be forced to queue memory access requests. Such queueing of memory access requests may increase the latency of memory accesses, which in turn may have a negative impact on the performance of the processor-based system.
To address this issue, memory bandwidth compression schemes may be employed to achieve memory bandwidth savings by reducing the bandwidth consumed by a given memory access. Some memory bandwidth compression schemes make use of compression indicators (CIs) that explicitly indicate a compression status of a corresponding memory block that is read from or written to in a system memory. For ease of access, the CIs may be kept in a memory area that is conventionally utilized by an error correcting code (ECC) mechanism as a storage area for ECC data words used for error detection and correction.
Some memory architectures employ what is known as a chipkill-correct ECC mechanism for providing error correction. A chipkill-correct ECC mechanism provides the ability to detect and correct the failure of multiple bits within a memory device by distributing bits of ECC data words across multiple physical memory chips, such that the failure of any single memory chip affects only a subset of the ECC bits per data word. Such chipkill-correct ECC mechanism may enable memory contents to be reconstructed despite a complete failure of one memory chip. However, the chipkill-correct ECC mechanism may also require the use of stronger ECC protection schemes that may consume more of the ECC storage area in which a CI can otherwise be kept. Thus, an alternative mechanism for providing an indication of compression status of a given memory block is desirable when using a memory architecture providing a chipkill-correct ECC mechanism.